1. Field of the Invention
This invention relates to non-volatile memory and to systems for storage of blocks of information.
2. Description of Related Art
A conventional non-volatile semiconductor memory such as a Flash memory includes one or more arrays of memory cells. FIG. 1A shows a conventional architecture for a Flash memory 100 including an array 110. The memory cells in array 110 are arranged in rows and columns and connected together by row lines 112 and column lines 113 (also referred to as word lines 112 and bit lines 113). Each row line 112 connects to the control gates of memory cells in an associated row, and each column line 113 connects to the drains of memory cells in an associated column. Flash memory array 110 is further divided into multiple sectors 115. Each sector 115 contains one or more columns of memory cells and has an associated source line 114 connected to the sources of the memory cells in the sector 115. Further associated with each memory array 110 are a row decoder 120, a column decoder 130, and a source decoder 140 that respectively connect to row lines 112, column lines 113, and source lines 114 of the array 110. Drivers (not shown) associated with row decoder 120, column decoder 130, and source decoder 140 bias row lines 112, column lines 113, and source lines 114 as required for erase, write, and read operations.
FIG. 1B shows another architecture for a Flash memory array 110xe2x80x2. Array 110 xe2x80x2 is similar to array 110 (FIG. 1A) but has row-based sectors 115xe2x80x2, instead of column based sectors. Each sector 115xe2x80x2 includes one or more rows of memory cell a source line 114xe2x80x2 connected to the sources of the memory cells in the sector 115xe2x80x2. A source decoder 140xe2x80x2 connects to and controls the voltage levels on source lines 114xe2x80x2 for erase, write, and read operations.
The memory arrays 110 and 110xe2x80x2 commonly store blocks of data. For example, a digitally encoded music player such as an MP3 music player can employ array 110 or 110xe2x80x2 to store data representing music or songs. The data for each song is stored in one or more sectors 115 or 115xe2x80x2, and each sector 115 or 115xe2x80x2 only stores data from one song. This arrangement permits a user to erase one song by erasing the sector or sectors associated with the song. The data associated with other songs, being stored in separate sectors, is not erased. A user can thus keep a favorite song while changing other songs. One drawback of this data arrangement is the wasted storage capacity resulting when data for a song only partly fills a sector so that some memory cells store no data. Sectors can be made smaller to reduce the average amount of wasted data storage. But, smaller sectors require a Flash memory to include more sectors for the same amount of storage, and the increase in the number of sectors increases circuit overhead. Accordingly, providing the greatest possible effective storage capacity per integrated circuit area requires balancing wasted memory cells in large sectors against increased overhead for small sectors.
Another concern or drawback of the conventional Flash memory architectures is the accumulation of disturbances of the threshold voltages of memory cells. With either array 110 or 110xe2x80x2, row decoder 120 and column decoder 130 respectively apply signals to a selected row line and a selected column line to write to or read from a selected memory cell. For a write operation, the voltages on the selected row and column lines are high and combine to change the threshold voltage of the selected memory cell, thereby writing a data value. The high row and column voltages can disturb the threshold voltages of unselected memory cells connected to the selected row line or the selected column line. These disturbances of the threshold voltages (i.e., write disturbs) can accumulate over time.
For an erase operation, source decoder 140 or 140xe2x80x2 and row decoder 120 establish in a selected sector a voltage difference between the control gates and the sources of the memory cells while the drains float. The voltage difference causes Fowler-Nordheim tunneling that lowers the threshold voltages of the memory cells in the selected sector, to an erased state. Typically, the source decoder applies a positive voltage to the source line 114 or 114xe2x80x2 for a selected sector, and row decoder 120 applies ground or a negative voltage to the row lines associated with the selected sector. For array 110, row lines 112 connect to memory cells in sectors 115 not being erased. Accordingly, erasing the selected sector can disturb the threshold voltages of memory cells in other sectors of the array 110. These disturbances of the threshold voltages (i.e., erase disturbs) can accumulate over time.
Particular problems arise if data remains in some sectors while other sectors of the array are repeatedly erased and programmed. In this case, the accumulated write and erase disturb can change the threshold voltages of memory cells in sectors storing long term data. Such disturbance can become intolerable in a multi-bit-per-cell memory. In a multi-bit-per-cell memory, each memory cell stores N bits of information and requires 2N distinguishable threshold voltage windows corresponding to the possible N-bit values. As N increases, the threshold voltage windows narrow, and the disturbance of the threshold voltages becomes more difficult to accommodate.
Another problem arises because the memory cells in sectors that are erased frequently age differently from memory cells in sectors that are rarely erased. To compensate for aging or endurance effects, a memory can include circuits that adjust erase, write, or read voltages to compensate for the effects of aging. Different types of compensation can be required for different sectors because the memory cells in different sectors have different histories and have aged differently. Some memories incorporate complex circuitry that monitors the number of erase operations for each sector and operates each sector according to its history. U.S. Pat. Nos. 5,172,338 and 5,163,021, entitled xe2x80x9cMulti-State EEPROM Read and Write Circuits and Techniquesxe2x80x9d, describe Flash memory including circuitry that compensates for differences in aging in different sectors. Such circuitry requires extra overhead, increases circuit complexity, and therefore can increase the cost of a Flash memory.
In accordance with the invention, a non-volatile memory uses a data management process or arrangement that is not sector-based. This improves storage efficiency because data blocks can be stored without unused storage cells between data blocks. To erase one or more data block from an array, data blocks from the array that are to be saved are read and stored temporarily in a storage device, such as a main memory or a hard disk drive of a computer system connected to the non-volatile memory. The entire memory array is then erased, and the data blocks from the storage device are rewritten in the memory, with the amount of storage originally allocated to the erased data blocks now being available for new data blocks. This data arrangement does not subject any memory cells to a large accumulated write or erase disturbances because all data is read from the array and freshly re-written back after other data blocks in the array are erased. Thus, the accumulated program disturb is limited to only that accumulated from filling the array with data at most once. Additionally, the separate sectors do not have different endurance histories that must be accounted for to extend the life of the memory. A single count of the number of erase operation performed on an array can control voltages used during erase, write, or read operation to extend the usable life of the memory.
One embodiment of the invention is a method for operating a semiconductor memory such as a multi-bit-per-cell Flash memory. The method includes: storing portions of a plurality of data blocks in an array in the memory; selecting one or more of the data blocks for erasure; reading from the array data from data blocks that are not selected for erasure; erasing the array; and writing into the memory the data read from the array. The data that were read from the array can be stored while erasing the array so that writing into the memory writes at least a portion of the data blocks back into the erased array. The array can be sectorless for simultaneously erasing all memory cells in the array or can be partitioned into separately erasable sectors that are erased in a sequential, parallel, or pipelined manner. To maximize storage utilization, the data blocks are written at consecutive addresses in the array, without regard for boundaries between sectors.
Another embodiment of the invention is a system for storage of data blocks. The system includes a first memory that is a non-volatile semiconductor memory such as a multi-bit-per-cell Flash memory and a computer system connected to the first memory. The computer system can be a personal computer that includes a storage device such as a disk drive and a processor that executes file management procedure. Executing the file management procedure includes: identifying a plurality of data blocks at least partially stored in an array in the first memory; selecting one or more of the data blocks for erasure; reading from the array data from data blocks that are not selected for erasure; storing in the storage device the data read from the array; erasing the array; and writing into the first memory the data from the storage device. In an example application, the data blocks represent music, and the first memory is the memory of a portable player of digitally-encoded music. The file management procedure can write the data from the storage device and data from new data blocks into the erased array. When writing, the data blocks are stored at consecutive physical addresses in the array, without regard for boundaries between sectors.
Yet another embodiment of the invention is a non-volatile memory that includes arrays of memory cells, local circuits, and global circuits. Each array includes row lines, column lines, and a source line, wherein the row lines, the column lines, and the source line of each array are isolated from the row lines, the column lines, and the source line of the other arrays. Each local circuit is associated with and coupled to a corresponding one of the arrays. The local circuits implement erase, write, and read operations in the corresponding array, wherein the erase operation erases all memory cells in the corresponding array. Each local circuit can maintain a single count of the number of erasures of the associated array and can use the count to select voltages used during erase, write, or read operations.
The global circuits connect to and coordinate the local circuits for input and output of data from the memory. To achieve a high bandwidth, the global circuits coordinate the local circuit to simultaneously write a plurality of multi-bit values in a plurality of the arrays and/or coordinate the local circuit to simultaneously read a plurality of multi-bit values from a plurality of the arrays.